For the past few years, instead of using a silicon channel in a conventional thin film transistor (TFT), an oxide semiconductor which is utilized in the TFT is another option. Because the oxide semiconductor TFT has an electrical characteristic of high carrier mobility as a low-temperature poly-silicon semiconductor TFT and an electrical uniformity as an amorphous silicon semiconductor TFT, the active matrix flat panel display in which the oxide semiconductor TFTs are applied gradually becomes a mainstream technique in the market.
Generally, at least six mask processes are required to produce a TFT which utilizes oxide semiconductors (such as indium gallium zinc oxide semiconductor, and so on). In a conventional TFT array, it is required to add a mask to form a connective hole in an insulating layer between the metal layers, so that a double-metal design in which a metal layer is directly stacked on another metal layer is formed.
FIG. 1A˜FIG. 1G are sectional structure views illustrating a conventional TFT array. As shown in FIG. 1A, a substrate 102 of the TFT array 10 can be divided into a TFT area 104 and a signal wire (scanning wire or data wire) area 106. A patterned first metal layer 108 is formed in the TFT area 104 and the signal wire area 106 of the substrate 102. The patterned first metal layer 108 in the TFT area 104 is used as a gate electrode of the TFT and the patterned first metal layer 108 in the signal wire area 106 is used as a metal conductive wire for signal transmitting. Then, as shown in FIG. 1B, a first insulating layer 110 is formed to cover the patterned first metal layer 108 in the TFT area 104 and the signal wire area 106 respectively. Thereafter, an oxide semiconductor layer 112 is formed on the first insulating layer 110 of the TFT area 104, as shown in FIG. 1C. Then, as shown in FIG. 1D, a second insulating layer 113 is formed on the oxide semiconductor layer 112 and the first insulating layer 110 and the second insulating layer 113 in the TFT area 104 is etched to expose a portion of the oxide semiconductor layer 112 to be several connective points 114 for source electrode and drain electrode. Furthermore, in the next process step, the first insulating layer 110 and the second insulating layer 113 in the signal wire area 106 are etched to expose a portion of the first metal layer 108 to be a connective hole 115, as shown in FIG. 1E.
Subsequently, as shown in FIG. 1F, a patterned second metal layer 116 is formed on the second insulating layer 113, the exposed oxide semiconductor layer 112 and the exposed first metal layer 108, and the second metal layer 116 is directly and electrically connected with the first metal layer 108 in the signal wire area 106. By the direct connection of the second metal layer 116 and the first metal layer 108 in the signal wire area 106, a double-metal layer structure is formed to reduce the wire resistance in the signal wire area 106. Finally, as shown in FIG. 1G, a passivation (PV) layer 118 is formed on the second metal layer 116. According to the conventional semiconductor process steps shown in FIG. 1A˜FIG. 1G, it is required to add the extra process step shown in FIG. 1E and the manufacturing cost is increase as a result.
Therefore, a need is arisen to achieve the purpose to reduce the resistance of the signal wire without adding an extra mask as well as without increasing additional manufacturing cost in the TFT array manufacturing process.